1. Field of the Invention
The invention relates generally to a component of a motherboard in a PC system and more particularly to an apparatus that supports both synchronous dynamic random access memory module and the double data rate dynamic random access memory module.
2. Description of the Related Art
Digital information is often stored in dynamic random access memory (DRAM). One type of DRAM transfers information synchronously with a clock signal. This type of DRAM is referred to as synchronous DRAM (SDRAM). SDRAM provides a burst read access (when programmed for burst length of 4). In case of 64-bit data bus interface system, such a transfer involves 32 bytes of data per SDRAM access. Currently PC systems typically use such as arrangement.
SDRAM transfers information once every clock cycle of the clock signal, such as the rising edge of the clock signal. Nevertheless, DDR DRAM transfers data on each edge of the clock signal (i.e., twice every clock cycle of the clock signal), thus doubling the peak throughput of the memory device as compared with SDRAM. DDR DRAM thus provides a burst of eight data transfers on every burst read access (when programmed for burst length of 4). As a result, the operation speed of the memory can be increased.
The operation difference between the synchronous dynamic random access memory and the double data rate dynamic random access memory is as follows. (1) The SDRAM works in normal clock signal, and the DDR DRAM works in differential clock signal. (2) The VDD of SDRAM is 3.3V, and the VDDQ of DDR DRAM is 2.5V. (3) SDRAM does not require a reference voltage, and the DDR DRAM requires a reference voltage of xc2xd VDDQ. (4) The data bus connected to SDRAM is a normal CMOS logic, and the data bus connected to DDR DRAM is a series stub terminated logic 2 (SSTL132). (5) The data bus connected to SDRAM does not require a terminated voltage VTT, and the data bus connected to DDR DRAM requires a terminated voltage VTT to absorb the reflected electric wave. (6) The data bus connected to SDRAM does not require a pull-up resistor, while the data bus connected to DDR DRAM requires a pull-up resistor. The superiority of the DDR DRAM includes its double data rate.
Currently, the motherboard supports either the SDRAM module or the DDR DRAM module. Cause of the memory module slot cannot support simultaneously both the SDRAM and the DDR DRAM. Also, support for both memory technologies would avoid obstacles to upgrading memory within a computer system. Thus, a technique is needed to provide compatibility for both SDRAM and DDR DRAM within a common system.
According to one embodiment of the principle of the present invention, a synthesizer comprises terminator of which the conduction is controllable. By applying the synthesizer to a motherboard, the user has the great flexibility in using different memory modules.
The invention is embodied in an synthesizer comprising a first signal terminal, a second signal terminal, a first enable pin, a terminator, a first electronic switch and a second electronic switch. The first and the second signal terminals are used for external connection. The first electronic switch has one terminal coupled to the first signal terminal and the other terminal coupled to the terminator. A control terminal of the first electronic switch is coupled to the first enable pin to control whether the terminator is conducted with the first signal terminal by the first enable pin. The second electronic switch has one terminal coupled to the first signal terminal and the other terminal coupled to the second signal terminal. The control terminal of the second electronic switch is coupled to the first enable pin to control whether the first and the second signal terminals are conducted with each other.
The above synthesizer further comprises a first source pin. The terminator has a first terminal and a second terminal. The first terminal of the terminator is connected to the first source pin, and the second terminal of the terminator is connected to the first electronic switch. The synthesizer can also comprise a second source pin. The first source pin and the second source pin are located in symmetric positions of the package of the synthesizer, and the first source pin is coupled to the second source pin. The first and the second source pins can also be formed on the same side of the package with an uppermost and lowermost
symmetric position. Thus, the source pins of the synthesizer and other synthesizers can be connected in series. The synthesizer can also comprise a second enable pin. The first enable pin and the second enable pin are located in symmetric positions of the package of the synthesizer. The first enable pin is coupled to the second enable pin. The above electronic switches can be made of transmission gate.
The invention further provides a motherboard that supports memory module slots both with and without a terminator. The motherboard comprises a first memory module slot, a second memory module slot, a synthesizer coupled to the first and the second memory module slots and a control chip set. The first memory module slot is used to connect a first memory module and requires a terminator for operation. The second memory module slot is used to connect a second memory module. The synthesizer is coupled to both the first and the second memory module slots. When the first memory module slot is inserted with the first memory module, the synthesizer provides an equivalent terminator. When the second memory module slot is embedded with the second memory module, the synthesizer does not provide an equivalent resistor. The control chip set is coupled to the first memory module slot and the synthesizer. When the first memory module is embedded in the first memory module slot, the control chip set controls the operation mode of the first memory module.
In the above motherboard, the first memory module includes a double data rate dynamic random access memory, while the second memory module includes a synchronous dynamic random access memory. The motherboard further comprises a voltage modulator coupled to the synthesizer to provide a terminal voltage and a clock generator coupled to the first and the second memory module slots. When the first memory module is embedded in the first memory module slot, a differential clock signal is generated. When the second memory module is embedded in the second memory module slot, a normal clock signal is generated.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.